FPGA programming using System Generator

FPGA programming using System Generator
(LED Blinking)

For programming the FPGA using system generator we required two software

1.MATLAB

2.Xilinx

step 1: Install both softwares

step 2: configured MATLAB for system generator

 Step 3: after successful configuration, open MATLAB software,open simulink and you can see xilinx         .            blockset get added in simulink library.

 

 Now you are ready for programming

• create new model file, file-new-model 

• from xilinx blockset select and drag blocks from library to simulink program file and wired  them all.

• double click on system generator block,

          system generator block converts simulink model into HDL codes
          compilation: folder name "netlist" get created in project folder and stores converted hdl files
          part: select the target FPGA device
         check "create testbench", so that testbench file get generate. we can use this file to verify correctness   of generated HDL code. 

              Clocking: 

              FPGA clock period: set it according to target FPGA board. my board support 100MHz.      .             frequency so time period becomes 10 ns
              Clock pin Location: FPGA pin where 100MHZ frequency get generated (varies from board to     .             board)
 

•  double click on counter block, select number of bits.

•  double click slice block, this block is useful for selecting a particular bit/pin number. since the output of counter is 4 bit and I want to work on only MSB bit I made following selections.

           (more number of counter bit = lesser the frequency on MSB bit)
           for more clarification refer the clock divider circuit on my blog page. so if you want delay of 1  .           second, make number of bits equals to 27 in counter block. 

•  gateway out: use to specify output pin of FPGA. in my case LED is connected to P15 pin .

•  save the file.

•  run the simulink model

• double click on scope block, if everything is correct then following window will pop up.

        hence simulation is correct

• double click on system generator block

• click on generate

• go to your project file, there you will find folder "netlist"

•  "netlist" folder contains all HDL files. open Xilinx ISE project file

• you can check the correctness of generated HDL file using testbench 

•  Double click on simulate behavioral model

Output of Testbench simulation.

• Double click on generate programming file, it will generate .bit format file / .bin format file, both are use for programming FPGA.

•  
• double click on configure target device. Download .bit/.bin file into FPGA using iMPACT

Download project files