VHDL code for Half Adder code with UCF file

 Simple Half Adder code with UCF file

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity half_adder is
Port ( A : in  STD_LOGIC;
 B : in  STD_LOGIC;
SUM : out  STD_LOGIC;
 CARRY : out  STD_LOGIC);
end half_adder;

architecture Behavioral of half_adder is

begin
SUM<=(A XOR B);
CARRY<=(A AND B);
end Behavioral;

UCF file

--UCF file should be configure before embedding the code in to FPGA kit
--F15, F16 are input pins connected to switches
--D12, C11 are output pins connected to LEDS
-- pin configuration may vary according to FPGA board manufactures.

net "A"    loc = "F15";
net "B"    loc = "F16";
net "SUM"    loc = "D12";
net "CARRY"    loc = "C11";