VHDL code for generating clock of desire frequency

Simple code to generate clock

-- you can generate clock of any frequency using this simple code
--this code generate square wave of frequency 40 MHz

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity frq25 is
port(clk_25:out std_logic);
end frq25;

architecture Behavioral of frq25 is
signal temp: std_logic:='0';
begin
temp<=not temp after 20 ns;
clk_25<=temp;
end Behavioral;

-- Test Bench

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY tt1 IS

END tt1;

ARCHITECTURE behavior OF tt1 IS

    COMPONENT frq25

    PORT(

         clk_25 : OUT  std_logic

        );

    END COMPONENT;

   

     --Outputs

   signal clk_25 : std_logic;

BEGIN

    -- Instantiate the Unit Under Test (UUT)

   uut: frq25 PORT MAP (

          clk_25 => clk_25

        );

   -- Stimulus process

   stim_proc: process

   begin       

      -- hold reset state for 100 ns.

      wait for 100 ns;   

 end process;

END;

Code to convert clock frequency from 100MHz to 40 MHz

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity frequency_generator is
port(sys_clk,clr:in std_logic; pixel_clk: out std_logic);
end frequency_generator;

architecture Behavioral of frequency_generator is
--signal a: std_logic;
signal b,c,d: std_logic:='0';
begin
p1:process(sys_clk)
begin
if clr='1' then
b<='0';
elsif (sys_clk'event and sys_clk='1') then
b<= not(b) ;
end if;
end process p1;
c<=b;

p2:process(c)
begin
if clr='1' then
d<='0';
elsif (c'event and c='1') then
d<= not(d) ;
end if;
end process p2;
pixel_clk<=d;
end Behavioral;