VHDL coding: VHDL code for clock divider

Clock Divider Circuit

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

entity clock_divider is

port(clk_in,clr:in std_logic;
clk_out:out std_logic;
clk_out_50MHz:out std_logic;
clk_out_25MHz :out std_logic;
clk_out_12_5MHz :out std_logic;
clk_out_6MHz:out std_logic;
clk_out_3MHz:out std_logic;
clk_out_1_6MHz:out std_logic;
clk_out_781KHz:out std_logic;
clk_out_390KHz:out std_logic;
clk_out_195KHz   :out std_logic;
clk_out_98KHz :out std_logic;
clk_out_49KHz:out std_logic;
clk_out_24KHz:out std_logic;
clk_out_12KHz:out std_logic;
clk_out_6_1KHz :out std_logic;
clk_out_3KHz:out std_logic;
clk_out_1_5KHz:out std_logic;
clk_out_763Hz:out std_logic;
clk_out_382Hz:out std_logic;
clk_out_191Hz:out std_logic;
clk_out_95Hz :out std_logic;
clk_out_48Hz:out std_logic;
clk_out_24Hz:out std_logic;
clk_out_12Hz :out std_logic;
clk_out_6Hz :out std_logic;
clk_out_3Hz :out std_logic;
clk_out_1_5Hz:out std_logic;
clk_out_0_75Hz :out std_logic);

end clock_divider;

architecture Behavioral of clock_divider is

signal temp:std_logic_vector(27 downto 0);

begin
process(clk_in, clr)
begin

if clr='1' then
temp<=X"0000000";
elsif clk_in'event and clk_in='1' then
temp<=temp+1;
end if;
end process;

clk_out_50MHz <=temp(0);-- out clock = 50 MHz                0.00002 ms
clk_out_25MHz <=temp(1);-- out clock = 25 MHz                0.00004 ms
clk_out_12_5MHz<=temp(2);-- out clock = 12.5 MHz               0.00008 ms
clk_out_6MHz<=temp(3);-- out clock = 6.25 MHz                0.00016 ms
clk_out_3MHz<=temp(4);-- out clock = 3.125 MHz            0.00032 ms
clk_out_1_6MHz<=temp(5);-- out clock = 1.5625 MHz           0.00064 ms
clk_out_781KHz<=temp(6);-- out clock = 781.25 KHz           0.00128 ms
clk_out_390KHz<=temp(7);-- out clock = 390.625 KHz           0.00256 ms
clk_out_195KHz <=temp(8);-- out clock = 195.3125 KHz          0.00512 ms
clk_out_98KHz <=temp(9);-- out clock = 97.656525 KHz        0.01024 ms
clk_out_49KHz<=temp(10);-- out clock = 48.828125 KHz        0.02048 ms
clk_out_24KHz<=temp(11);-- out clock = 24.4140625 KHz    0.04096 ms
clk_out_12KHz<=temp(12);-- out clock = 12.20703125 KHz    0.08192 ms
clk_out_6_1KHz <=temp(13);-- out clock = 6.1035 KHz            0.16384 ms
clk_out_3KHz<=temp(14);-- out clock = 3.05175 KHz        0.32768 ms
clk_out_1_5KHz<=temp(15);-- out clock = 1.5258 KHz            0.65536 ms
clk_out_763Hz <=temp(16);-- out clock = 762.9394 Hz        1.31072 ms
clk_out_382Hz <=temp(17);-- out clock = 381.47 Hz            2.62144 ms
clk_out_191Hz<=temp(18);-- out clock = 190.7348 Hz           5.24288 ms
clk_out_95Hz <=temp(19);-- out clock = 95.3674 Hz            10.48576 ms
clk_out_48Hz<=temp(20);-- out clock = 47.6837 Hz            20.97152 ms
clk_out_24Hz<=temp(21);-- out clock = 23.84185 Hz           41.94304 ms
clk_out_12Hz <=temp(22);-- out clock = 11.92 Hz            83.88608 ms
clk_out_6Hz <=temp(23);-- out clock = 5.96 Hz                167.785 ms
clk_out_3Hz <=temp(24);-- out clock = 2.98 Hz                335.54432 ms
clk_out_1_5Hz<=temp(25);-- out clock = 1.49 Hz                671.14 ms
clk_out_0_75Hz <=temp(26);-- out clock = 0.745 Hz            1.34 s

end Behavioral;

-- Clock Divider circuit Testbench

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY clock_divs IS
END clock_divs;

ARCHITECTURE behavior OF clock_divs IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT clock_divider
    PORT(
         clk_in : IN std_logic;
         clr : IN std_logic;
         clk_out : OUT std_logic;
         clk_out_50MHz : OUT std_logic;
         clk_out_25MHz : OUT std_logic;
         clk_out_12_5MHz : OUT std_logic;
         clk_out_6MHz : OUT std_logic;
         clk_out_3MHz : OUT std_logic;
         clk_out_1_6MHz : OUT std_logic;
         clk_out_781KHz : OUT std_logic;
         clk_out_390KHz : OUT std_logic;
         clk_out_195KHz : OUT std_logic;
         clk_out_98KHz : OUT std_logic;
         clk_out_49KHz : OUT std_logic;
         clk_out_24KHz : OUT std_logic;
         clk_out_12KHz : OUT std_logic;
         clk_out_6_1KHz : OUT std_logic;
         clk_out_3KHz : OUT std_logic;
         clk_out_1_5KHz : OUT std_logic;
         clk_out_763Hz : OUT std_logic;
         clk_out_382Hz : OUT std_logic;
         clk_out_191Hz : OUT std_logic;
         clk_out_95Hz : OUT std_logic;
         clk_out_48Hz : OUT std_logic;
         clk_out_24Hz : OUT std_logic;
         clk_out_12Hz : OUT std_logic;
         clk_out_6Hz : OUT std_logic;
         clk_out_3Hz : OUT std_logic;
         clk_out_1_5Hz : OUT std_logic;
         clk_out_0_75Hz : OUT std_logic
        );
    END COMPONENT;


   --Inputs
   signal clk_in : std_logic := '0';
   signal clr : std_logic := '0';

     --Outputs
   signal clk_out : std_logic;
   signal clk_out_50MHz : std_logic;
   signal clk_out_25MHz : std_logic;
   signal clk_out_12_5MHz : std_logic;
   signal clk_out_6MHz : std_logic;
   signal clk_out_3MHz : std_logic;
   signal clk_out_1_6MHz : std_logic;
   signal clk_out_781KHz : std_logic;
   signal clk_out_390KHz : std_logic;
   signal clk_out_195KHz : std_logic;
   signal clk_out_98KHz : std_logic;
   signal clk_out_49KHz : std_logic;
   signal clk_out_24KHz : std_logic;
   signal clk_out_12KHz : std_logic;
   signal clk_out_6_1KHz : std_logic;
   signal clk_out_3KHz : std_logic;
   signal clk_out_1_5KHz : std_logic;
   signal clk_out_763Hz : std_logic;
   signal clk_out_382Hz : std_logic;
   signal clk_out_191Hz : std_logic;
   signal clk_out_95Hz : std_logic;
   signal clk_out_48Hz : std_logic;
   signal clk_out_24Hz : std_logic;
   signal clk_out_12Hz : std_logic;
   signal clk_out_6Hz : std_logic;
   signal clk_out_3Hz : std_logic;
   signal clk_out_1_5Hz : std_logic;
   signal clk_out_0_75Hz : std_logic;

   -- Clock period definitions
   constant clk_in_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: clock_divider PORT MAP (
          clk_in => clk_in,
          clr => clr,
          clk_out => clk_out,
          clk_out_50MHz => clk_out_50MHz,
          clk_out_25MHz => clk_out_25MHz,
          clk_out_12_5MHz => clk_out_12_5MHz,
          clk_out_6MHz => clk_out_6MHz,
          clk_out_3MHz => clk_out_3MHz,
          clk_out_1_6MHz => clk_out_1_6MHz,
          clk_out_781KHz => clk_out_781KHz,
          clk_out_390KHz => clk_out_390KHz,
          clk_out_195KHz => clk_out_195KHz,
          clk_out_98KHz => clk_out_98KHz,
          clk_out_49KHz => clk_out_49KHz,
          clk_out_24KHz => clk_out_24KHz,
          clk_out_12KHz => clk_out_12KHz,
          clk_out_6_1KHz => clk_out_6_1KHz,
          clk_out_3KHz => clk_out_3KHz,
          clk_out_1_5KHz => clk_out_1_5KHz,
          clk_out_763Hz => clk_out_763Hz,
          clk_out_382Hz => clk_out_382Hz,
          clk_out_191Hz => clk_out_191Hz,
          clk_out_95Hz => clk_out_95Hz,
          clk_out_48Hz => clk_out_48Hz,
          clk_out_24Hz => clk_out_24Hz,
          clk_out_12Hz => clk_out_12Hz,
          clk_out_6Hz => clk_out_6Hz,
          clk_out_3Hz => clk_out_3Hz,
          clk_out_1_5Hz => clk_out_1_5Hz,
          clk_out_0_75Hz => clk_out_0_75Hz
        );

   -- Clock process definitions
   clk_in_process :process
   begin
        clk_in <= '0';
        wait for clk_in_period/2;
        clk_in <= '1';
        wait for clk_in_period/2;
   end process;

   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100 ns.
      wait for 100 ns;
        clr<='1';
              wait for 100 ns;

clr<='0';
    wait for 100 ns;

      -- insert stimulus here

      wait;
   end process;

END;

--Testbench Waveform

VHDL coding

VHDL code for clock divider

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