--switch output won't go high till button is remained press for atleast 3 clock cycles
-- here is the code for 6 switches
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Switch_debounce is
port(cclk,clr: in std_logic;
sw_in: in std_logic_vector(5 downto 0);
sw_out: out std_logic_vector(5 downto 0));
end Switch_debounce;
architecture Behavioral of Switch_debounce is
signal delay1,delay2,delay3:std_logic_vector(5 downto 0);
begin
process(cclk,clr)
begin
if clr='1' then
delay1<="000000";
delay2<="000000";
delay3<="000000";
elsif cclk'event and cclk='1' then
delay1<=sw_in;
delay2<=delay1;
delay3<=delay2;
end if;
end process;
sw_out<=delay1 and delay2 and delay3;
end Behavioral;
--Testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY switch_debounce_testbench IS
END switch_debounce_testbench;
ARCHITECTURE behavior OF switch_debounce_testbench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Switch_debounce
PORT(
cclk : IN std_logic;
clr : IN std_logic;
sw_in : IN std_logic_vector(5 downto 0);
sw_out : OUT std_logic_vector(5 downto 0)
);
END COMPONENT;
--Inputs
signal cclk : std_logic := '0';
signal clr : std_logic := '0';
signal sw_in : std_logic_vector(5 downto 0) := (others => '0');
--Outputs
signal sw_out : std_logic_vector(5 downto 0);
-- Clock period definitions
constant cclk_period : time := 2 ms;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Switch_debounce PORT MAP (
cclk =>cclk,
clr =>clr,
sw_in =>sw_in,
sw_out =>sw_out
);
-- Clock process definitions
cclk_process :process
begin
cclk <= '0';
wait for cclk_period/2;
cclk <= '1';
wait for cclk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
clr<='1';
wait for 100 ns;
clr<='0';
-- insert stimulus here
sw_in(1<='0';
wait for 2 ms;
sw_in(1)<='1';
wait for 3 ms;
sw_in(1)<='0';
wait for 4 ms;
sw_in(1)<='1';
wait for 8 ms;
sw_in(1)<='0';
wait;
end process;
END;
-- Waveform
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