VHDL code for FIFO

--vhdl code for FIFO (first input first output)
--here FIFO is able to store 16 data of 8bit

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fifo is
port(data_in:in std_logic_vector(7 downto 0);clk,en:in std_logic;
fifo_out:out std_logic_vector(7 downto 0));
end fifo;

architecture Behavioral of fifo is
type memory_type is array(1 to 16) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
signal fifo1:memory_type;

begin
process(clk,en)
begin

if en='1' then
if clk'event and clk='1' then
fifo1<=data_in & fifo1(1 to 15);
fifo_out<=fifo1(16);
end if;
end if;
end process;

end Behavioral;