VHDL code for addition of 4_BIT_ADDER with user library

-- create library name as ‘work’

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity fulladd is

    Port ( cin : in  STD_LOGIC;

           x : in  STD_LOGIC;

           y : in  STD_LOGIC;

           s : out  STD_LOGIC;

           coutt : out  STD_LOGIC);

end fulladd;

architecture logicfunc of fulladd is

begin

s<=(x xor y xor cin);

coutt<=(x and y)or(x and cin)or(y and cin);

end logicfunc ;

library ieee;

use ieee.std_logic_1164.all;

package fulladd_package is

component fulladd

port(cin,x,y:in std_logic;

     s,coutt:out std_logic);

end component;

end fulladd_package;

--use library name as ‘work’

library work;

use work.fulladd_package.all;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity adder4 is

port(cin:in std_logic;

      x0,x1,x2,x3:in std_logic;

     y0,y1,y2,y3:in std_logic;

      s0,s1,s2,s3:out std_logic;

      cout:out std_logic);

end adder4;

architecture  structure of adder4 is

signal c1,c2,c3:std_logic;

begin

stage0:fulladd port map (cin,x0,y0,s0,c1);

stage1:fulladd port map (c1,x1,y1,s1,c2);

stage2:fulladd port map (c2,x2,y2,s2,c3);

stage3:fulladd port map (c3,x3,y3,s3,cout);

end structure;