VHDL code for simple addition of two four bit numbers

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity adder is
    Port ( a,b : in  STD_LOGIC_VECTOR (3 downto 0);
           c : out  STD_LOGIC_VECTOR (4 downto 0));
end adder;

architecture Behavioral of adder is

begin
c<=(('0'&a)+('0'&b));

end Behavioral;


Output: