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FPGA programming using System Generator

FPGA programming using System Generator
(LED Blinking)

For programming the FPGA using system generator we required two software

1.MATLAB

2.Xilinx

step 1: Install both softwares

step 2: configured MATLAB for system generator

 Step 3: after successful configuration, open MATLAB software,open simulink and you can see xilinx         .            blockset get added in simulink library.

 

 Now you are ready for programming

• create new model file, file-new-model 

• from xilinx blockset select and drag blocks from library to simulink program file and wired  them all.

• double click on system generator block,

          system generator block converts simulink model into HDL codes
          compilation: folder name "netlist" get created in project folder and stores converted hdl files
          part: select the target FPGA device
         check "create testbench", so that testbench file get generate. we can use this file to verify correctness   of generated HDL code. 

              Clocking: 

              FPGA clock period: set it according to target FPGA board. my board support 100MHz.      .             frequency so time period becomes 10 ns
              Clock pin Location: FPGA pin where 100MHZ frequency get generated (varies from board to     .             board)
 

•  double click on counter block, select number of bits.

•  double click slice block, this block is useful for selecting a particular bit/pin number. since the output of counter is 4 bit and I want to work on only MSB bit I made following selections.

           (more number of counter bit = lesser the frequency on MSB bit)
           for more clarification refer the clock divider circuit on my blog page. so if you want delay of 1  .           second, make number of bits equals to 27 in counter block. 

•  gateway out: use to specify output pin of FPGA. in my case LED is connected to P15 pin .

•  save the file.

•  run the simulink model

• double click on scope block, if everything is correct then following window will pop up.

        hence simulation is correct

• double click on system generator block

• click on generate

• go to your project file, there you will find folder "netlist"

•  "netlist" folder contains all HDL files. open Xilinx ISE project file

• you can check the correctness of generated HDL file using testbench 

•  Double click on simulate behavioral model

Output of Testbench simulation.

• Double click on generate programming file, it will generate .bit format file / .bin format file, both are use for programming FPGA.

•  
• double click on configure target device. Download .bit/.bin file into FPGA using iMPACT

Download project files

MIMAS V2 spartan-6 board, Design and implementation of delay module

Design and implementation of delay module on MIMAS V2 spartan-6 FPGA board

MIMAS V2 spartan-6 FPGA board has input clock frequency of 100 Mhz. using frequency divider

(100000000/2^27 )=0.745 Hz i.e 1.342 sec

Hence this VHDL code gives approximate 1 second delay

--Main Code--

entity DELAY1S is
    Port ( CLK,CLR : in  STD_LOGIC;
           CLK_OUT : OUT STD_LOGIC);
end DELAY1S;

architecture Behavioral of DELAY1S is
SIGNAL Q:STD_LOGIC_VECTOR( 27 DOWNTO 0 );
BEGIN
PROCESS (CLR, CLK)
BEGIN
IF CLR='1' THEN
Q<=X"0000000";
ELSIF CLK'EVENT AND CLK='1' THEN
Q<=Q+1;
END IF;
END PROCESS;
CLK_OUT<=Q(26);
end Behavioral;

--Test Bench--

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY test1 IS
END test1;

ARCHITECTURE behavior OF test1 IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT DELAY1S
    PORT(
         CLK : IN  std_logic;
         CLR : IN  std_logic;
         CLK_OUT : OUT  std_logic
        );
    END COMPONENT;
   

   --Inputs
   signal CLK : std_logic := '0';
   signal CLR : std_logic := '0';

     --Outputs
   signal CLK_OUT : std_logic;

   -- Clock period definitions
   constant CLK_period : time := 10 ns;
--   constant CLK_OUT_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: DELAY1S PORT MAP (
          CLK => CLK,
          CLR => CLR,
          CLK_OUT => CLK_OUT
        );

   -- Clock process definitions
   CLK_process :process
   begin
        CLK <= '0';
        wait for CLK_period/2;
        CLK <= '1';
        wait for CLK_period/2;
   end process;

--   CLK_OUT_process :process
--   begin
--        CLK_OUT <= '0';
--        wait for CLK_OUT_period/2;
--        CLK_OUT <= '1';
--        wait for CLK_OUT_period/2;
--   end process;
--

   -- Stimulus process
   stim_proc: process
   begin       
      -- hold reset state for 100 ns.
        
      wait for 100 ns;
clr<='1';
         wait for 100 ns;
clr<='0';
     

      wait;
   end process;

END;

Output waveform:

####UCF file####

#input clock frequency
NET "CLK" LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz;

# onBoard DIP SWITCHES
NET "CLR" LOC = "C17"  | IOSTANDARD = LVCMOS33  | DRIVE = 8  | SLEW = FAST | PULLUP;

# ON BOARD LEDS
NET "CLK_OUT" LOC = "T18"  | IOSTANDARD = LVCMOS33  | DRIVE = 8  | SLEW = FAST;

Download

Click here to download project file

My Published Paper

My Published Papers

Paper Title: Design of Sobel operator based image edge detection algorithm on FPGA
Published by: IEEE
Abstract: Real-time image processing applications requires processing on large data of pixels in a given timing constraints. Reconfigurable device like FPGAs have emerged as promising solutions for reducing execution times by deploying parallelism techniques in image processing algorithms. Implementation of highly parallel system architecture, parallel access of large internal memory banks and optimization of processing element for applications makes FPGA an ideal device for image processing system. Edge detection is basic tool used in many image processing applications for extracting information from image. Sobel edge detection is gradient based edge detection method used to find edge pixels in image. This paper presents a design of a Sobel edge detection algorithm to find edge pixels in gray scale image. Xilinx ISE Design Suite-14 software platforms is used to design a algorithm using VHDL language. MATLAB software platform is used for obtaining pixel data matrix from gray scale image and vice versa. Xilinx FPGAs of family Vertex-5 are more suitable for image processing work than Spartan-3 and Spartan-6.

Link: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6949951&queryText%3Dchaple

Paper Title: Image Edge Detection using Sobel Operator Based on FPGA
Published by: Elsevier Publication
Abstract: Image processing algorithm implemented in reconfigurable device like FPGA have
emerged as most viable solution for improving performance of image processing systems. On FPGA
highly parallel system architecture can be implemented to achieve real-time requirement of system
and processing element can be optimized for the application. Edge detection is a fundamental tool
used in image processing applications to extract information from image frames. Sobel edge detection
is method to find edge pixel in an image. This paper presents the design of gradient based edge
detection algorithm using Sobel operator on reconfigurable device FPGA. VHDL language is used to
developed edge detection algorithm. This paper focused on edge detection of gray scale image.

Link: http://www.elsevierst.com/conference_book_download_chapter.php?cbid=87#chapter34






 

Project Ideas

Project 1. FPGA based fast OMR (optical mask recognisation) sheet reader system

Description : OMR sheet is a paper with circle marks, one need to fill or darken the circles to select options. Mainly use to fill officials forms or to answer multiple choice questions. OMR sheets are use for fast and error less processing on user data.  FPGA is very powerful tool in real-time image processing. with FPGA it is possible to achieve processing on 30 OMR sheet per second.

System Requirements: 
a. Xilinx or Altera FPGA Board
b. Xilinx ISE or Altera quartus (Software development tool)
c. Camera (monochrome CMOS camera)
d. VGA monitor (Any PC monitor)

Project 2. FPGA based fast faulted product removal system ( example: removal of cracked soap from conveyor belt)

Description :  FPGAs have large number of input/output ports and hence can be very useful in automation system design. FPGA supports various industrial protocols and one can design his own protocol in FPGA.
By designing image edge detection system on FPGA, it is possible to detect cracks on Soap and then can be remove from conveyor belt. By using FPGA, processing on one image can be completed in 20 ms time and hence near about 20 sample of soap per second can be scan for defects.

System Requirements: 
a. Xilinx or Altera FPGA Board
b. Xilinx ISE or Altera quartus (Software development tool)
c. Camera (monochrome CMOS camera)
d. VGA monitor (Any PC monitor)


Project 3. FPGA based Robot control 

Description : FPGA based wireless control of robot system can be  used to for various application of military and industrial uses.

System Requirements: 
a. Xilinx or Altera FPGA Board
b. Xilinx ISE or Altera quartus (Software development tool)
c. Camera (monochrome CMOS camera)
d. zigbee wireless transmitter and receiver
  

VHDL code for register

--N-bit register with clear and load

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity reg is
generic(N : integer := 8);
port( load : in STD_LOGIC; a : in STD_LOGIC_VECTOR(N-1  downto 0);
clk : in STD_LOGIC; clr : in STD_LOGIC; b :out STD_LOGIC_VECTOR(N-1  downto 0));
end reg;

architecture reg of reg is
begin
process(clk, clr)
begin
if clr = '1' then
b <= (others=> '0');
elsif clk'event  and clk = '1' then
if load= '1' then
b<= a;
end if;
end if;
end process;
end reg;


output:

 

how to read content from text file and How to write content in text file in VHDL

--PROGRAM TO READ CONTENT FROM ONE FILE AND WRITE IT IN to ANOTHER FILE

--THIS PROGRAM HAS TO BE WRITTEN IN TESTBENCH MODULE

--INPUT AND OUTPUT text FILES SHOULD BE PRESENT IN YOUR PROJECT FOLDER

 

library ieee;

use ieee.std_logic_1164.all;

use STD.Textio.all;--PACKAGE CONTAIN FUNTIONS RELATED TO FILE READ/WRITE OPERATION

 

entity FA_TESTS is

end FA_TESTS;

architecture behavioral of FA_TESTS is

begin

 

process

file infile :text; --DEFINES INPUT FILE_HANDLE AND TYPE OF FILE

file outfile :text;--DEFINES INPUT FILE_HANDLE AND TYPE OF FILE

variable buff: line;--VARIABLE WITH TYPE LINE TO READ COMPLETE LINE/ROW AT A TIME

 

begin

file_open(infile,"gnc.txt",read_mode); --OPEN FILE NAME "GNC.TXT' TO READ CONTENT FROM THAT FILE

file_open(outfile,"gncc.txt", write_mode);--OPEN FILE NAME "GNCC.TXT" TO WRITE CONTENT TO THAT FILE

for i in 1 to 4 loop  --AS INPUT FILE "GNC.TXT" CONTAIN CONTENT OF 4 LINE

readline(infile, buff); --TO READ A LINE FROM INPUT FILE

writeline(outfile,buff);--TO WRITE A LINE TO OUTPUT FILE

end loop;

file_close(infile);--NECESSARY TO CLOSE OPEN FILE

file_close(outfile); --NECESSARY TO CLOSE OPEN FILE

wait;--TO HALT THE PROGRAM / TO AVOID INFINITE EXECUTION OF PROGRAM

end process;

 

end  behavioral;