MIMAS V2 spartan-6 board, Design and implementation of delay module

Design and implementation of delay module on MIMAS V2 spartan-6 FPGA board

MIMAS V2 spartan-6 FPGA board has input clock frequency of 100 Mhz. using frequency divider

(100000000/2^27 )=0.745 Hz i.e 1.342 sec

Hence this VHDL code gives approximate 1 second delay

--Main Code--

entity DELAY1S is
    Port ( CLK,CLR : in  STD_LOGIC;
           CLK_OUT : OUT STD_LOGIC);
end DELAY1S;

architecture Behavioral of DELAY1S is
SIGNAL Q:STD_LOGIC_VECTOR( 27 DOWNTO 0 );
BEGIN
PROCESS (CLR, CLK)
BEGIN
IF CLR='1' THEN
Q<=X"0000000";
ELSIF CLK'EVENT AND CLK='1' THEN
Q<=Q+1;
END IF;
END PROCESS;
CLK_OUT<=Q(26);
end Behavioral;

--Test Bench--

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY test1 IS
END test1;

ARCHITECTURE behavior OF test1 IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT DELAY1S
    PORT(
         CLK : IN  std_logic;
         CLR : IN  std_logic;
         CLK_OUT : OUT  std_logic
        );
    END COMPONENT;
   

   --Inputs
   signal CLK : std_logic := '0';
   signal CLR : std_logic := '0';

     --Outputs
   signal CLK_OUT : std_logic;

   -- Clock period definitions
   constant CLK_period : time := 10 ns;
--   constant CLK_OUT_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: DELAY1S PORT MAP (
          CLK => CLK,
          CLR => CLR,
          CLK_OUT => CLK_OUT
        );

   -- Clock process definitions
   CLK_process :process
   begin
        CLK <= '0';
        wait for CLK_period/2;
        CLK <= '1';
        wait for CLK_period/2;
   end process;

--   CLK_OUT_process :process
--   begin
--        CLK_OUT <= '0';
--        wait for CLK_OUT_period/2;
--        CLK_OUT <= '1';
--        wait for CLK_OUT_period/2;
--   end process;
--

   -- Stimulus process
   stim_proc: process
   begin       
      -- hold reset state for 100 ns.
        
      wait for 100 ns;
clr<='1';
         wait for 100 ns;
clr<='0';
     

      wait;
   end process;

END;

Output waveform:

####UCF file####

#input clock frequency
NET "CLK" LOC = V10 | IOSTANDARD = LVCMOS33 | PERIOD = 100MHz;

# onBoard DIP SWITCHES
NET "CLR" LOC = "C17"  | IOSTANDARD = LVCMOS33  | DRIVE = 8  | SLEW = FAST | PULLUP;

# ON BOARD LEDS
NET "CLK_OUT" LOC = "T18"  | IOSTANDARD = LVCMOS33  | DRIVE = 8  | SLEW = FAST;

Download

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